1. Field of Invention
This invention relates to a new and improved buried layer metal-insulator-semiconductor memory capacitor device for use as a target element with electron beam accessed memories and to the method of its use in an electronic memory system.
2. Background of Invention
Electron beam addressable memories for use as the main or peripheral memory of a computer system have been under investigation for a number of years. One known form of a workable electron beam addressable memory employing a metal-insulator-semiconductor capacitor structure as the memory element target was first described in an article entitled "Electron Beam Detection of Charge Storage in MOS Capacitors", appearing in Applied Physics Letters, Volume 16, No. 4, pages 147-149, February, 1970 and has been disclosed further in U.S. Pat. Nos. 3,736,571, issued May 29, 1973 and in U.S. Pat. No. 3,886,530, issued May 27, 1975. Electron beam addressable memories which employ multi-layered semi-conductors having p-n junctions through which reverse current flow is induced by injection of electrons by an electron beam probe, have been described in U.S. Pat. Nos. 3,550,094, issued Dec. 22, 1970, in U.S. Pat. No. 3,761,895, issued Sept. 25, 1973 and in an article entitled "A Semiconductor Non-volatile Electron Beam Accessed Mass Memory" appearing in the Proceedings of the IEEE, Volume 63, No. 8, August, 1975, pgs. 1230-1239.
The electron beam addressable memories employing built in multi-layered semiconductor target structures described in the last mentioned U.S. patents and publication all employ metal-insulator-semiconductor memory target structures which require external conductive electrical connection access to two or more semiconductor layers of opposite conductivity type and an electrically conducting overlayer for application of suitable biases during operation of the memory. To overcome the requirement in an electron beam accessible memory of employing three or more terminals in capacitive read-out, metal-insulator-semiconductor target structures having two or more different conductivity type semiconductors layers defining a p-n junction, the present invention was devised.